May-June 2021, Vol. 6, No. 5-6, pp. 95-100.
A low power full adder design with digital to analog converter circuit by generic 250nm devices
A. Sriram*, R. Saranya
Department of Electronics and Communication Engineering,Arasu Engineering College, Kumbakonam – 612501. India.
*Corresponding author’s e-mail:contactsriramnow@gmail.com
Abstract
In recent trends most of the digital circuits are combinations of full adders and multiplexer. In past many reported that adders, multiplexer are suffered from the problems of voltage swing and high noise when operated at low voltage. Authors have discussed 8-bit multiplexer design employing CMOS full adder using Double Pass Transistor and multi output carry look ahead logic. DPL adder avoids the noise edge problem and speed deprivation at low value of supply voltages associated with complementary pass transistor logic circuits. Consequently new design methodologies are being implemented in which CMOS logic full adder is one of the proposed circuit having low power consumption and high speed. For this we adopted AND and OR gates. The investigation is carried out with simulation runs on GENERIC250nm. These gates are regulated for obtaining sum output with DPL. In this paper we implemented multiplexer by using CMOS logic full adder.
Keywords: Full adder; Generic 250 nm; AND gate; OR gate.
References
- Syed Z, Hassan N. Design and simulation of enhanced 64-bit Vedic multiplier, IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies, 11-13 Oct. 2017, Aqaba, Jordan.
- Lamba B, Sharma A. A review paper on different multipliers based on their different performance parameters, 2nd International Conference on Inventive Systems and Control, 19-20 Jan. 2018, Coimbatore, India.
- Sriram A, Abikayal K. Low Power Flash ADC and DAC Optimized with Pull down Circuit Control. International Journal of Modern Science and Technology 2016;1(9)311-17.
- Sriram A, Deepan P. Effective Optimization of Network Reliability using New Adaptive Genetic Algorithm. International Journal of Modern Science and Technology 2016;1(4):115-20.
- Jiang, Y, Al-Sheraidah A, Wang Y, Sha E, Chung J-G. A novel multiplexerbased low- power full adder. IEEE Transactions on Circuits and Systems II: Express Briefs 2004;51:345-48.
- Soniya, Suresh Kumar. A Review of Different Typeof Multipliers and Multiplier Accumulator Unit, International Journal of Emerging Trends and Technology in Computer Science 2013;2:364-68.
- Dillikumar, Charan kumar K, Bharathi M. Low power multiplexer base full adder using pass transistor logic, International Journal of Advanced Research in Computer Engineering and Technology 2012;1:291-96.
- Sriram A, Abikayal K. Design of Reversible Comparator using Reversible Gates with Encoding Technique. International Journal of Modern Science and Technology 2017;2(6):238-42.
- Sriram A, Indhu S. Design and Performance Analysis of Inexact-Speculative Han Carlson Adder. International Journal of Modern Computation, Information and Communication Technology 2018;1(1):8-14.
- Sriram A, Thivagar T. Hand Gesture and Voice Controlled Smart Vehicle. International Journal of Modern Science and Technology 5(6);164-47.
- A. Sriram, and P. Deepan P. Effective Optimization of Network Reliability using New Adaptive Genetic Algorithm. International Journal of Modern Science and Technology. 2016;1(4):115-20.
- Aravind Kumar M, Ranga Rao O, Dileep M, Pradeep Kumar Reddy CV, Man KP. Performance Evaluation of Different Multipliers in VLSI using VHDL. International Journal of Advanced Research in Computer and Communication Engineering 2016;5:6-11.
- Saha A, Pal D, Chandra M. Low power 6-GHz wave-pipelined 8b×8b multiplier,” IET Circuits. Devices & Systems 2013;7:124-40.
- Saha A, Chandra M. Benchmarking of DPL Based 8b×8b Novel Wave-Pipelined Multiplier. International Journal of Electronics Letters 2017;5:115-28.
- Hang G, Zhou X. Novel CMOS ternary flip-flops using double pass-transistor logic. IEEE International Conference on Electric Information and Control Engineering 2011, Wuhan, China, 15-17April 2011.
- Hang G, Zhou X. Novel CMOS static ternary logic using double pass-transistor logic,” 2nd IEEE International Conference on Information Science and Engineering 2010, 4-6 December 2010.
- Vudadha C, Srinivas MB. Design methodologies for ternary logic circuits. 48th IEEE International Symposium on MultipleValued Logic , 16-18 May 2018.
- Sriram A, Sudhakar T.D. Technology revolution in the inspection of power transmission lines - A literature review. 2021 7th International Conference on Electrical Energy Systems (ICEES), Chennai, India, 2021, pp. 256-262, doi: 10.1109/ICEES51510.2021.9383707.
- Sriram A, Dhasarathi M. Effective Multiplexer Power-Delay Space Design using Generic 250 nm Device,” International Journal of Modern Science and Technology 2019;4(11):281-85.
- Sriram A, Sudhakar T.D. Protection of Power Transmission Lines Using Intelligent Hot Spot Detection. 2019 Fifth International Conference on Electrical Energy Systems (ICEES), Chennai, India, 2019, pp. 1-6, doi: 10.1109/ICEES.2019.8719290.
- Sriram A, Sudhakar T.D. Technology revolution in the inspection of power transmission lines - A literature review. 2021 7th International Conference on Electrical Energy Systems (ICEES), 2021, pp. 256-262, doi: 10.1109/ICEES51510.2021.9383707.
- Anbalagan S, Sudhakar T.D. Protection of Power Transmission Lines Using Intelligent Hot Spot Detection. 2019 Fifth International Conference on Electrical Energy Systems (ICEES), 2019, pp. 1-6, doi: 10.1109/ICEES.2019.8719290
International Journal of Modern Science and Technology