​​May-June 2021, Vol. 6, No. 5-6, pp. 95-100. 

​​​A low power full adder design with digital to analog converter circuit by generic 250nm devices

A. Sriram*, R. Saranya
Department of Electronics and Communication Engineering,Arasu Engineering College, Kumbakonam – 612501. India.

​​​*Corresponding author’s e-mail:contactsriramnow@gmail.com

​Abstract

​In recent trends most of the digital circuits are combinations of full adders and multiplexer. In past many reported that adders, multiplexer are suffered from the problems of voltage swing and high noise when operated at low voltage. Authors have discussed 8-bit multiplexer design employing CMOS full adder using Double Pass Transistor and multi output carry look ahead logic. DPL adder avoids the noise edge problem and speed deprivation at low value of supply voltages associated with complementary pass transistor logic circuits. Consequently new design methodologies are being implemented in which CMOS logic full adder is one of the proposed circuit having low power consumption and high speed. For this we adopted AND and OR gates. The investigation is carried out with simulation runs on GENERIC250nm. These gates are regulated for obtaining sum output with DPL. In this paper we implemented multiplexer by using CMOS logic full adder.

Keywords: Full adder; Generic 250 nm; AND gate; OR gate.

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International Journal of Modern Science and Technology

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ISSN 2456-0235