ISSN 2456-0235

International Journal of Modern Science and Technology

November 2019, Vol. 4, No. 11, pp 281-285. 

​​Effective Multiplexer Power-Delay Space Design using Generic 250 nm Device

M. Dhasarathi, A. Sriram
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam – 612501. Tamilnadu, India.

​​*Corresponding author’s e-mail:


High speed and low power is utmost requirement of today’s VLSI systems and digital signal processing applications. In this paper, we have discussed 8-bit multiplexer design employing CMOS full adder, full adder using Double Pass Transistor and multi output carry Look ahead logic. DPL adder avoids the noise edge problem and speed deprivation at low value of supply voltages associated with complementary pass transistor logic circuits. Multi output carry look ahead adder leads to significant enhancement in the speed of the overall circuitry. The investigation is carried out with simulation runs on GENERIC 250 nm. Finally, the design guidelines are derived to select the most suitable topology for the desired applications. Investigation reveals that multiplexer design using multi output carry look ahead adder proves to be more speed efficient in comparison with the other two considered design strategies.

Keywords: Multiplexer; Generic 250 nm; CMOS; full adder.


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