​​​​​International Journal of Modern Science and Technology, Vol. 2, No. 6, 2017, Pages 238-242. 

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​Design of Reversible Comparator using Reversible Gates with Encoding Technique  

K. Abikayal, A. Sriram
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam - 612501. India. 

​​​​*Corresponding author’s e-mail: abikadhirvel@gmail.com

​Abstract
Reversible logic has an alternate design technique to a conventional logic resulting in low power consumption and circuit delay. Comparators are a key element in most digital systems. In this project, 4-bit comparator based on priority encoder circuit is designed. Reversible logic gates performed the multiple operations in a single unit. This design consist mainly the feyaman gates. It is one type of reversible logic gates. The reversibility recovers bits loss from the designated input-output mapping and its applications have spread in various technologies like quantum computing nanotechnology and low power design. The 4-bit comparator using reversible gates to reduce optimization parameters like number of constant inputs, garbage outputs and quantum cost is verified by using Xilinx ISE software. 

​​Keywords: Reversible logic; Comparators; Priority encoders; Logical delay path; Quantum cost; Low power.

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International Journal of Modern Science and Technology

INDEXED IN 

ISSN 2456-0235