International Journal of Modern Science and Technology
International Journal of Modern Science and Technology, Vol. 2, No. 5, 2017, Pages 217-222.
Implementation of Low Power, Delay and Area Efficient Shifters for Memory Based Computation
S. Soundarya*, K. Prasanna
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam-612501. India.
*Corresponding author’s e-mail: email@example.com
The efficient memory based computation is essential in DSP applications. The optimized Area is carried out for LUT’s, and then delay will also reduce. In this paper, the barrel shifter which requires only one clock cycle for “n” number of shifts and it can shift all of the outputs up to three positions to the right side (LSB). In this brief, APC-OMS technique is used for LUT size reduction. The design also consists of Arbiter Shifter to select the order of access to shared resource among asynchronous requests. The FIFO algorithm is used in arbiter shifter for receiving the request and grant signals. This proposed system shows less area, delay and power compared to the existing shift register. The design synthesis and power analysis are carried out by using Xilinx 12.1 version software.
Keywords: Anti-symmetric coding; Odd Multiple Storage; First in First out; Look up table; Least significant bit.
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