International Journal of Modern Science and Technology


​​​​​International Journal of Modern Science and Technology, Vol. 2, No. 5, 2017, Pages 217-222.


Implementation of Low Power, Delay and Area Efficient Shifters for Memory Based Computation  

S. Soundarya*, K. Prasanna
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam-612501. India.
​​*Corresponding author’s e-mail:

The efficient memory based computation is essential in DSP applications. The optimized Area is carried out for LUT’s, and then delay will also reduce. In this paper, the barrel shifter which requires only one clock cycle for “n” number of shifts and it can shift all of the outputs up to three positions to the right side (LSB). In this brief, APC-OMS technique is used for LUT size reduction. The design also consists of Arbiter Shifter to select the order of access to shared resource among asynchronous requests. The FIFO algorithm is used in arbiter shifter for receiving the request and grant signals. This proposed system shows less area, delay and power compared to the existing shift register. The design synthesis and power analysis are carried out by using Xilinx 12.1 version software.

​​Keywords: Anti-symmetric coding; Odd Multiple Storage; First in First out; Look up table; Least significant bit.


  1. Anusya S, Bhubaneswari PR. Design and Implementation of Motion Artifact Reduction Asic for wearable​ ​ECG​ ​recording.​ ​American-Eurasian​ ​Journal​ ​of​ ​Scientific​ ​Research.​​ ​2014;​10​(3):​154-159​.
  2. Bhavin DM, Altaf D. VHDL Implementation of 8Bit Vedic Multiplier using Barrel Shifter. International​ ​Journal​ ​of​ ​Scientific​ ​Research​ ​and​ ​Development.​ ​2014;2​​(1):156-158.
  3. Feng C, Lu Z. Addressing Transient and Permanent Faults in Noc with efficient Fault Tolerant Deflection Router. IEEE Transactions on Very  Large Integration Systems. 2013;​21(6):​1053​ ​-​ ​1066​. 
  4. Liya P,  Reen P. Modified APcOMS technique for Memory Based Computing. Global Colloquium in Recent Advancement and Effectual Researchers in Engineering Science and Technology. 2016. 
  5. Manoj MK, Sunita P. Analysis of Different Multiplication Algorithm and FPGA Implementation of Recursive Barrel ShifterMethod for Multiplication. International Research Journal of​ ​Engineering​ and​Technology. 2016;3(1):1141-1142. 
  6. Mallela U, Ravi J. Design of Digital  FIR Filter Using LUT Based Multiplier. International​ ​Journal​ ​of ​Electronics​ Communication​ ​and​ ​Computer​  Technology. 2013;3(5):477-479. 
  7. Mohanamma MP, Vamsee K. Design and Implementation of LUT Based Multiplier using APCOMS Technique. International Journal of Scientific Research of Development.  2013;1(7):476-479. 
  8. Pavar Kumar, P, Neelima R. Digital FIR  Filter Implementation using Combined APC-OMS Technique.​ ​International​Journal​ ​of​ ​VLSI​ ​and​ ​Embedded​ ​Systems. 2014;4:​06122​. 
  9. Pragati S, Anchal K. Anita D, Pallavi G. Barrel Shifter. International Journal of Science and Engineering and​ ​Technology. 2014;2(7):1434-1440. 
  10. Kamal R, Yadav N. Noc and Bus  Architecture a Comparsion. International Journal of Engineering​ ​Science​ ​and​ Technology. 2012;4(4):1438-1442. 
  11. Pappachan R, Vijayakumar V. Design and Analysis of a 4Bit Low Power Barrel Shifter in 20 nm​ ​FINFET​ Technology.​ ​International​ ​Journal​ ​of​ ​Engineering​ ​and​ ​Sciences. 2013;2​(3):​17-25. 
  12. Ramya, Sudha M. LUT Optimization  using Combined APCOMS Technique for Memory Based Computation. International Journal of Computer Applications in Engineering Sciences. 2013;3:119-127. 
  13. Sreelakshmi K, Srinivasa Rao A. An Advanced and Area Optimized LUT Design using APC and OMS.​ ​International​ ​Journal​ ​of​ ​​ ​Computer​ ​Science​ ​and​ ​Information​ ​Technologies. 2012;3:4265-4269. 
  14. AbhisekT, Ketan D, Patel N. An Approach for Implementation of Bus Arbitration Techniques. International​ ​Journal​ ​of​ ​Scientific​ ​Research​ ​of​ ​Development. 2016;4(2):112-116.

ISSN 2456-0235