​​​​​​Vol. 2, No. 10, 2017, pp. 345-353. 


Power Analysis of Sense Amplifier Designs for low voltage Memories   

K. Gavaskar*, G. Ravivarma
Department of Electronics and Communication Engineering, Kongu Engineering College, Erode, Tamilnadu – 638 060. India.
​​*Corresponding author’s e-mail: gavas.20@gmail.com

Abstract
A memory array structure consists of matrix of SRAM (Static Random Access Memory) cells in which each memory cell in an array structure can be accessed by row and a column decoder. Sense amplifier plays a vital role in memory array structure.The job of a sense amplifier is to sense the bit lines and retrieve the stored data in a memory.Reducing the power consumption of the sense amplifier reduces the power consumption of the whole circuit.The above explained operation can be carried out using Synopsys-Custom Designer tool by applying some optimization techniques like stack, sleep transistor sleepy stack and leakage feedback techniques.

Keywords: Sense amplifier; Power; Low voltage; Memories. 

References

  1. Babu A, Ravindra JVR, Lalkishore K. Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits. Circ Syst Signal Pr 2015;34(13):60-69.
  2. Gavaskar K, Ragupathy US. An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications. Asian J Res Soc Sci Humn 2017;7(1):2249-7315.
  3. Corsonello P, Lanuzza M, Perri S. Gate-level body biasing technique for high speed sub-threshold CMOS logic gates. Int J Circ Theory Appl 2014;42(4):65–70.
  4. Aggarwal B, Gupta M, Gupta AK. A very high performance self-biased cascode current mirror for CMOS technology. Analog Integr Circuits Signal Process 2013;75(4):67-74.
  5. Kumar M, Hussain A, Paul SK. An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Sub threshold Leakage. Circ Syst Signal Pr 2013;4(2):431-437.
  6. Leela Rani V, Latha M. Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits. Circ Syst Signal Pr 2016;35(8):4139–4152.
  7. Lim W, Lee I, Sylvester D, Blaauw D. Battery less Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic. IEEE Int Solid-State Circ Conference 2015;146– 147.
  8. Raj N, Singh AK, Gupta AK. Low-Voltage Bulk- Driven Self -Biased Cascade Current Mirror With Bandwidth Enhancement. Electron. Lett 2014;50(1):23–25.
  9. Lorenzo R, Chaudhury S. Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS circuits. Circ Syst Signal Pr 2016;36(5):2654–2671.
  10. Sonam R, Srivastava R. Dynamic Threshold MOS (DTMOS) and its Application. Int J Sci, Eng Res 2016;5(6):69-74.
  11. Tikyani M, Pandey M. A New Low-Voltage Current Mirror Circuit with Enhanced Bandwidth. Int Conf Comput Intelli Comm Netw 2011;31(41):42–46.
  12. Gavaskar K, Priya S. Design of efficient low power stable 4-bit memory cell. Int J Com Appl 2013;84(1):0975–8887.
  13. Shalini S, Shyam A. Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell. Wireless Pers Comm 2017;96(1):0929-6212​​. 

International Journal of Modern Science and Technology

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ISSN 2456-0235