International Journal of Modern Science and Technology
October-November 2021, Vol. 6, No. 10-11, pp. 171-174.
A High Speed and Low Leakage 12-T SRAM for Truncated Power Applications
P. S. Vinishya*, K. Solangkili
Department of Electronics and Communication Engineering, Arasu Engineering College, Chennai Main Road, Kumbakonam, India.
*Corresponding author’s e-mail: email@example.com
High speed and low leakage constraints are put on the 12-T SRAM cell. Truncated power integrated circuits are massively fascinating for portable and wearable applications. A twelve-transistor SRAM circuit is proposed in this paper. The SRAM cells are designed with dual gate transistor for every column in order to achieve low leakage and high speed operation. An error margin is reduced up to 10% based on device size and capacitive load during read-out scheme. The data stability as well as read /write ability is based on standard topology which in turn reduces read /write delay.
Keywords: System on Chip; 12T SRAM; Integrated circuits; Wireless sensor application.
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