ISSN 2456-0235

International Journal of Modern Science and Technology


​​​​​​​September-October 2020, Vol. 5, No. 9-10, pp. 246-250. 

​​Design of carry select adder using 8T-full adder and 4T-multiplexer

G. Nirmal Raja*, K. Gavaskar
Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, Erode. India.

​​*Corresponding author’s   


Design of carry select adder using 8T-full adders and 4T-multiplexers are proposed in the present work. These circuits are designed to have low power and reduced transistor size compared to regular circuits. Each one of the proposed designs has its advantages of area and power consumption. CSLA is the most suitable among conventional adder’s structures because it performs fast addition operation at low cost. The proposed CSLA has reduced transistor count and has lesser power consumption as well as compared to regular CSLA and modified CSLA. The present was also study proposed the area and power utilization of modified circuits. Simulations are done in tanner tool 180 nm technology.

Keywords: CSLA; RCA; Full adder; Multiplexer; XOR gates; Low power.


  1. Sanjana B, Ragini K. Design of a Novel High-Speed-and Energy-Efficient 32-Bit Carry-Skip Adder. Innovations in Electronics and Communication Engineering. 2019, Springer. p. 335-343.
  2. Muralidharan V, Kumar NS. Design And Implementation of Low Power and High Speed Multiplier using Quaternary Carry Look-Ahead Adder. Microprocessors and Microsystems. 2020;75:103054.
  3. John Alex E, Vijayaraj M. Energy Efficient BEC Modified Carry Select Adder Based PTMAC Architecture for Biomedical Processors. Intelligent Automation and Soft Computing. 2017;23(2):383-8.
  4. Balasubramanian P. Asynchronous carry select adders. Engineering science and Technology An international Journal. 2017. 20(3): p. 1066-1074.
  5. Tari HT, Zarandi AD, Reshadinezhad MR. Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders. Microelectronic Engineering. 2019;215:110980.
  6. Kumar N, Mittal P. Performance Investigation of 2: 1 Multiplexer using 90nm Technology Node for Low Power Application. International Conference on Electrical and Electronics Engineering (ICE3). IEEE 2020.
  7. Khan AA, Pandey S, Pathak J. A review paper on 3-T XOR cells and 8-T adder design in cadence 180nm. International Conference for Convergence for Technology-2014. IEEE 2014.
  8. Sarkar S, Sarkar S, Atta A, Pahari T, Majumdar N, Mondal S. 9T and 8T Full Subtractor Design Using Modified GDI and 3T XOR Technique, Advances in Computer, Communication and Control. 2019, Springer, Singapore; pp. 487-499.
  9. Kumar SS, Rakesh S. A Novel high-speed low power 9T full adder. Materials Today Proceedings 2020;24:1882-9.