​​​​​​​November 2020, Vol. 5, No. 11, pp. 251-265. 

​​A novel design and analysis of low power multipliers using full swing gate diffusion input method

R. Indhumathi*, K. Gavaskar, S. R. Nandhini, J. Raja Nandhini
Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, Erode. India.

​​*Corresponding author’s e-mail:indhuma2228@gmail.com   


In the present paper mainly focused on accuracy and power of different types of multipliers using full swing gate diffusion input (FSGDI) method. The main objective of this paper is to reduce the power consumption and improve the accuracy of the multipliers. In normal gate diffusion input method (GDI) required less transistors compared with full swing gate diffusion method. But cannot get the full level of output there is some charge sharing problem is occurred in GDI method. In FSGDI method the transistor counts gets increased compared with GDI method but there is no charge sharing problem is occurred. There are three types of multiplier was implemented using FSGDI method like conventional array multiplier, Vedic multiplier and Wallace tree multiplier. Based on the power results and performance analysis Wallace tree multiplier is efficient to design using Tanner tool version 13.

Keywords: Full swing gate diffusion input; Gate diffusion input; Array multiplier; Vedic multiplier; Wallace tree multiplier; Low power.


  1. Hussain I, Chaudhury S. A comparative   study   on the effects of technology nodes and logic         styles for low power high-speed VLSI applications.  International Nanoparticles 2020;12(2):122-30.
  2. Morgenshtein A. Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design. Journal of Integration 2014;4(1):62-70.
  3. Hussain I, Pandey SK, Chaudhury S.  Design and analysis of high performance multiplier circuit. Devices for Integrated Circuit Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 245-247, doi: 10.1109/DEVIC.2019.8783322.
  4. Bhardwaj K, Mane PS, Henkel J. Power-and area-efficient approximate wallace tree multiplier for error-resilient systems.  Fifteenth IEEE International Symposium on Quality Electronic Design. 2014.
  5. Jaiswal KB, Nithish Kumar V, Seshadri P, Lakshminarayanan G. Low power wallace tree multiplier using modified full adder, 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), Chennai, 2015, pp. 1-4, doi: 10.1109/ICSCN.2015.7219880.
  6. Sureka N, Porselvi R, Kumuthapriya K. An efficient high speed Wallace tree multiplier.  IEEE International Conference on Information Communication and Embedded Systems (ICICES). 2020;7: 962-975.
  7. Gavaskar K, Ragupathy US, Malini V. Design of Novel SRAM cell using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories. Wireless Personal Communications 2019;4:2311-39.
  8. Gavaskar K, Ragupathy US, Malini V, Proposed Design of 1KB Memory Array Structure  for   Cache Memories. Wireless Personal Communications, Springer. 2019;4:1-29.
  9. Abed S, Khalil Y, Modhaffar M. High-performance low-power approximate Wallace tree multiplier. International Journal of Circuits and Theory Applications 2018;46:2334-48.
  10. Shanmuganathan R, Brindhadevi K.         Comparative analysis of various types of multipliers for effective low power. Microelectronics Engineering 2019;214:28-37.
  11. Prashanthi M, Kyung KK, Minsu C. Novel Area-efficient Null Convention Logic based on CMOS and Gate Diffusion Input (GDI) Hybrid. Journal of Semiconductor Technology and Science 2020;20(1):127-34.
  12. Subba Rao K, Vassoudevan R. Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques. Journal of Computational and Theoretical Nanoscience 2020;4:1595-9.
  13. Sukhanya M, Gavaskar K. Functional verification environment for I2C master controller using system verilog, 4th  International Conference on Signal Processing, Communication and Networking (ICSCN), Chennai, 2017, pp. 1-6, doi: 10.1109/ICSCN.2017.8085732.
  14. Sukhanya M, Gavaskar K. Design and Verification of LTSSM in USB 3.0 Link  Layer  using  System verilog.  4th International Conference on Signal Processing, Communication and Networking (ICSCN), Chennai, 2017, pp. 1-6, doi: 10.1109/ICSCN.2017.8085689..
  15. Sarkar S, Sarkar S, Atta A, Pahari T, Majumdar N, Mondal S. 9T and 8T FullSubtractor Design using Modified GDI and 3T XOR Technique, Advances in Computer, Communication and Control. In: Biswas U., Banerjee A., Pal S., Biswas A., Sarkar D., Haldar S. (eds) Advances in Computer, Communication and Control. Lecture Notes in Networks and Systems, vol 41. Springer, Singapore. https://doi.org/10.1007/978-981-13-3122-0_49
  16. Tari HT, Zarandi AD, Reshadinezhad MR. Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders. Microelectronic Engineering. 2019;215:110980.
  17. Sanjana B, Ragini K. Design of a Novel High-Speed-and Energy-Efficient 32-Bit Carry-Skip Adder. In: Saini H., Singh R., Kumar G., Rather G., Santhi K. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, Vol 65. Springer, Singapore. https://doi.org/10.1007/978-981-13-3765-9_35

ISSN 2456-0235

International Journal of Modern Science and Technology