November 2020, Vol. 5, No. 11, pp. 251-265.
A novel design and analysis of low power multipliers using full swing gate diffusion input method
R. Indhumathi*, K. Gavaskar, S. R. Nandhini, J. Raja Nandhini
Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, Erode. India.
*Corresponding author’s e-mail:firstname.lastname@example.org
In the present paper mainly focused on accuracy and power of different types of multipliers using full swing gate diffusion input (FSGDI) method. The main objective of this paper is to reduce the power consumption and improve the accuracy of the multipliers. In normal gate diffusion input method (GDI) required less transistors compared with full swing gate diffusion method. But cannot get the full level of output there is some charge sharing problem is occurred in GDI method. In FSGDI method the transistor counts gets increased compared with GDI method but there is no charge sharing problem is occurred. There are three types of multiplier was implemented using FSGDI method like conventional array multiplier, Vedic multiplier and Wallace tree multiplier. Based on the power results and performance analysis Wallace tree multiplier is efficient to design using Tanner tool version 13.
Keywords: Full swing gate diffusion input; Gate diffusion input; Array multiplier; Vedic multiplier; Wallace tree multiplier; Low power.
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