ISSN 2456-0235

International Journal of Modern Science and Technology


​​​​​​​​​​​​March 2018, Vol. 3, No. 3, pp 59-64. 

​​Design and Power analysis of Decoders for Memory Array Structure

K. Gavaskar, V. Malini
Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai – 638060. India.
​​*Corresponding author’s e-mail:


Digital electronics circuits operate with digital signals so there performance is less subject to noise, signal attenuation and manufacturing tolerance. Digital system have prominent role in everyday life due to their ability to represent and manipulate discrete elements of information. Logic circuits for digital system may be combinational or sequential. A decoder is a combinational circuit that converts code into a set of signals. A binary code of n bits is capable of representing upto 2n distinct elements of coded information. The operation of the decoder may be clarified by the truth table. A decoder that generates the minterms of the function, together with an external OR gate that forms their logical sum, provides a hardware implementation of the function. A decoder with an enable input is referred to as decoder - demultiplexer. Three different decoders 1X2, 2X4 and 4X16 decoders are analyzed in this paper. Design metrics such as static power and dynamic power are taken into account. All the decoders were designed using SYNOPSYS EDA tool and simulated in 30nm technology. Simulation results shows that the 4X16 decoder has higher power dissipation than the other two decoders.

Keywords: Dynamic power; Static power; Decoder; Array structure; Memory.


  1. Soundarya S, Prasanna K. Implementation of low power, delay and area efficient Shifters for Memory Based Computation. . International Journal of Modern Science and Technology. 2017;2(5):217-222.
  2. Sivaranjini S, Kavitha G. Design of area efficient and low power carry select adder. International Journal of Modern Science and Technology. 2017;2(6):243-248.
  3. Gavaskar K, Ragupathy U S. An Efficient Design and Analysis of Low Power SRAM Memory Cell for Ultra Applications. Asian J Res Soc Sci Humn. 2017;7(1):962-975.
  4. Nayak D, Mahapatra.K. Current starving SRAM cell: A strategy to improve the cell   stability and power. Circ Syst Signal Pr. 2017;36(10):3047-3070.
  5. Babu A, Ravindra J V R. Design of Ultra Low Power PMOS and NMOS for Nano Scale VLSI circuits. Circ Syst Signal Pr. 2015;34(13):60-69.
  6. Leela Rani V, Latha M. Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits. Circ Syst Signal Pr. 2016;35(8):4139–4152.
  7. Abikayal K, Sriram A. Design of reversible comparator using Reversible Gates with Encoding Technique International Journal of Modern Science and Technology. 2017;2(6):238-242.
  8. Lee GG, Chen CF. High- Throughput Reconfigurable Variable Length Coding Decoder for MPEG-2 and AVC/H.264. J Sign Process Syst. 2016;82:27-40.
  9. Vikram AC, Azid SM. Resource Efficient LDPC Decoders for multimedia communication. Integ VLSI J. 2015;48:213-220.
  10. Shalini S, Shyam A. A Low Power Consuming 1KB (32X32) Memory Array Using Compact 7T SRAM cell. Wireless Pers Comm. 2017;96(1):1099-1109.
  11. Huyen PT, Sabooh A. High throughput partial parallel block layered decoding architecture for non binary LDPC codes. Integration the VLSI Journal. 2017;59:52-63.
  12. Wojciech S. Non binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation. Circ Syst Signal Pr. 2016;35:4060-4080.
  13. Pallavi S, Vanya A. Design and analysis of all optical half adder, half subtractor and 4 bit decoder based on SOA-MZI configuration. Opt Quant Electron. 2016;48:159.  
  14. Shiann-Rong K, Ping T. A Low Power Codeword Based Viterbi Decoder with Fine Grained Error Detection and Correction Techniques. Arab J Sci Eng. 2018;43:585-595.
  15. Gavaskar K, Ravivarma G. Power analysis of Sense Amplifier Designs for low voltage Memories. International Journal of Modern Science and Technology. 2017;2(10):345-353.