ISSN 2456-0235

International Journal of Modern Science and Technology


​​​​​International Journal of Modern Science and Technology, Vol. 2, No. 6, 2017, Pages 249-255. 

Reduction of Process Variation in Sub-threshold Logic Circuit using Adaptive Feedback Equalization  

R. Nithya*, P. Sathyaraj
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam - 612501. India. 
​​*Corresponding author’s e-mail:

Low energy or low powers are the primary constraint in the design of digital VLSI circuits in recent years. Minimum energy consumption can be achieved in digital circuits by operating it in the sub-threshold region. However this regime can only be achieved by proper body-biasing and transistor upsizing. Slow speed is the main drawback which can have a detrimental impact on the functionality of the circuits operating under low supply voltage. This becomes more frequent in scaled technology node where process variations are highly prevalent. Therefore mechanism to mitigate these timing errors in circuits is required. The proposal in this paper is to use variable threshold feedback equalizer circuit with combinational logic block to mitigate the timing constraint which can then be leveraged to reduce the propagation delay. As the part of analysis, a conventional D flip-flop is compared with a proposed equalized flip-flop using tanner EDA. The power and delay analysis of this feedback circuit is done using Xilinx software. 

​​Keywords: Feedback equalizer; Leakage energy component; Propagation delay; Sub-threshold.


  1. Pelgrom MJ, Duinmaijer AC, Welbers A. P. Matching properties of mos transistors. IEEE Journal of Solid-State Circuits. 2009;24:1433-1439.
  2. Verma N, Kwong J, Chandrakasan AP. Nanometer mosfet variation in minimum energy sub threshold circuits. IEEE Transactions on Electron Devices. 2008;55:163-174.
  3. Jayakumar N, Khatri SP. A variation-tolerant sub-threshold design approach. 42nd IEEE on Design Automation Conference. 2005; pp. 716-719.
  4. Liu B, Pourshaghaghi HR, Londono SM, de Gyvez JP. Process variation reduction for cmos logic operating at sub-threshold supply voltage. 14th Euromicro Conference on Digital System Design. 2011; pp. 135-139.
  5.  Wang A, Chandrakasan A. A 180-mv subthreshold fft processor using a minimum energy design methodology,” IEEE Journal of Solid-State Circuits. 2005;40:310-319.
  6. Kwong J, Ramadass YK, Verma N, Chandrakasan AP. A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter. IEEE Journal of Solid-State Circuits. 2009;44:115-126.
  7. Zhai B, Hanson S, Blaauw D, Sylvester D. Analysis and mitigation of variability in subthreshold design. Int. Symp. Low Power Electronics Design. 2005; pp. 20-25.
  8. Choi SH, Paul BC, Roy K. Novel sizing algorithm for yield improvement under process variation in nanometer technology. 41st Design Automation Conference. 2004; pp. 454-459.
  9. Lotze N, Ortmanns M, Manoli Y. Variability of flip-flop timing at sub-threshold voltages. IEEE Int. Symp. Low Power Electron. Design. 2008; pp. 221-224.
  10. Li D, Chuang PIJ, Nairn D, Sachdev M. Design and analysis of metastable-hardened flip-flops in sub-threshold region. Int. Symp. Low Power Electronics Design. 2011; pp. 157-162.
  11. Lotze N, Manoli Y. A 62 mV 0.13 μm CMOS standard-cellbased design technique using Schmitt-trigger logic. IEEE Journal of Solid-State Circuits. 2012;47:47-60.