International Journal of Modern Science and Technology
International Journal of Modern Science and Technology, Vol. 2, No. 6, 2017, Pages 243-248.
Design of area efficient and low power carry select adder
S. Sivaranjani*, G. Kavitha
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam - 612501. India.
*Corresponding author’s e-mail: firstname.lastname@example.org
High performance digital adders with less power consumption and reduced area are a fundamental design issues for advanced processors. Carry select adders is one of the fastest adder in many processors to perform fast arithmetic function. The speed of operations such an adder is limited by carry propagation from input to output. This project discusses about the implementation of Carry Select Adder (CSLA) with Binary to Excess-1 Code converters (BEC) and Multiplexer. The BEC is used to improve the speed of addition. The main advantage of BEC logic comes from the lesser number of logic gates than the Full Adder structure. The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power. The CSLA are simulated and synthesized using Xilinx ISE 12.1v software.
Keywords: Carry Select Adder; Ripple Carry Adder; Binary to Excess Code converters; Multiplexer.
- Ramkumar B, Harish MK. Low-Power and Area-Efficient Carry Select Adder. IEEE Transactions on Very Large Scale Integration Systems. 2012;20(2):371-375.
- Padma Devi, Ashima Girdher, Balwinder Singh. Improved Carry Select Adder with reduced area and Low power Consumption. International Journal of Computer Applications. 2010;3(4):14-18.
- Raut VG, Ashwini L. Design of Carry Select Adder for FIR Filter. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering. 2015;4(3):1348-1351.
- Charan Kumar B, Uday Kumar A. A 64-bit kogge stone carry save adder is designed for reducing area by using zero finding logic. International Journal of VLSI System Design and Communication Systems. 2017;5(1):8-11.
- Deepak Kumar P, Raksha C, Minal S. An Efficient VLSI Architecture for Carry Select Adder Without Multiplexer. International Journal of Computer Applications. 2015;127(93):37-40.
- Golda Hepzib K, Subha CP. A novel implementation of high speed modified brent kung carry select adder. 10th International Conference on Intelligent Systems and Control. Coimbatore, India. 2015.
- Nithin P, Udaya Kumar N, Bala Sindhuri K. Implementation of 16-bit Area Efficient Ling Carry Select Adder. International Journal of Advanced Information Science and Technology. 2016;5(9):57-63.
- Nithin P, Udaya Kumar N, Bala Sindhuri K. Implementation of 32-bit Carry Select Adder using Brent-Kung Adder. India Journal of Science and Technology. 2016;9(44);1-7.
- Shanigarapu L, Shrivastava BP. Low-Power and High Speed Carry Select adder. International Journal of Scientific and Research Publications. 2013;3(8);1-9.
- Sajesh Kumar U, Mohamed Saloj KK, Sajith K. Design and Implementation of Carry Select Adder without using Multiplexers. 1st International Conference on Emerging Technology Trends in Electronics, Communication and Networking. 2012.127(9);37-40.