International Journal of Modern Science and Technology, Vol. 2, No. 6, 2017, Pages 238-242.
Design of Reversible Comparator using Reversible Gates with Encoding Technique
K. Abikayal, A. Sriram
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam - 612501. India.
*Corresponding author’s e-mail: firstname.lastname@example.org
Reversible logic has an alternate design technique to a conventional logic resulting in low power consumption and circuit delay. Comparators are a key element in most digital systems. In this project, 4-bit comparator based on priority encoder circuit is designed. Reversible logic gates performed the multiple operations in a single unit. This design consist mainly the feyaman gates. It is one type of reversible logic gates. The reversibility recovers bits loss from the designated input-output mapping and its applications have spread in various technologies like quantum computing nanotechnology and low power design. The 4-bit comparator using reversible gates to reduce optimization parameters like number of constant inputs, garbage outputs and quantum cost is verified by using Xilinx ISE software.
Keywords: Reversible logic; Comparators; Priority encoders; Logical delay path; Quantum cost; Low power.
- Dharani C, Ravi J . A Review of Low Power High Speed Flash ADC. International Journal of Innovative Research in Computer and Communication Engineering. 2016;4(10):17457-17461.
- Anjaneyulu O, Pradeep T, Krishna Reddy CV. Design And Implementation Of Reversible Logic Based Bidirectional Barrel Shifter. IEEE Conference on Semiconductor Electronics, Kuala Lumpur, Malaysia: 2012. pp. 756-759.
- Ashwini D, Srikar D. An Optimal Approach of Priority Encoding Based Reversible Comparators. International Journal of Innovative Research in Technology. 2016;3(7):206-210.
- Ganguly A, Makerjee S. Implementation of 3 bit Flas Adc using Tunable Double Gate Mosfet. International Journal of Advanced Engineering and Global Technology. 2013;3(5):660-666.
- Latha C, Praveen Kumar V. Design of Reversible Comparator with Priority Encoding using Verilog HDL. International Journal and Magazine of Technology Management and Research. 2016;3(7):181-187.
- Ghosh K, Haque M. Design of Reversible Ternary Adder and Encoder Priority Encoder Circuits. IEEE International Conference on Communication And Signal Processing, 2016. pp. 6-8.
- Nagamani AN, Manu S, Vinoth kumar A. Design of Priority Encoding Based Reversible Comparators. IEEE International Conference on Electron Devices and Solid State Circuits, 2015. pp. 490-494.
- Sharma N, Manchanda R. Designing successive Approximation Register ADC by using Double Tail Comparator. International Journal of Scientific and Research. 2015;4(7):6-8.
- Pratik Kumar B, Arthi S. Optimized Study of one bit Comparator using Reversible Logie Gates. International Journal of Research in Engineering and Technology. 2013;2(9):111-116.
- Saleh AH, Ann GS, Behrooz P. Scalable Digital Cmos Comparator using a Parallel Prefix Tree. IEEE Transactions on Very Large Scale Integration Systems. 2012:21(11):108 -110.
International Journal of Modern Science and Technology